Memory devices, such as random access memory (RAM), read only memory (ROM), non-volatile memory (NVM) and the like are known in the art.
Reference is now made to FIG. 1 which is a schematic illustration of a virtual ground memory array, generally referenced 10, which is known in the art. Array 10 includes a plurality of memory cells 16, a plurality of word lines 12 and a plurality of bit lines 14.
The memory cells 16 are arranged in a matrix. Each of the memory cells 16 is also denoted by an index (x,y) which indicates its location within the matrix.
Each row of cells is integrally connected to a word line. For example, all of the cells in the first upper line of cells, from cell 16.sub.(1,1) to cell 16.sub.(M,1), are connected to word line 12.sub.1. Each column of cells is connected to two bit lines, one on either side. For example, all of the cells in the left column, from cell 16.sub.(1,1) to cell 16.sub.(1,N), are connected to bit line 14.sub.1, on one side (left) and to bit line 14.sub.2 on the other side (right). In general, a cell 16.sub.(x,y) is connected to word line 12.sub.y and to bit lines 14.sub.X and 14.sub.X+1.
Accordingly, tapping onto a selected word-line and two selected adjacent bit lines enables performing various procedures on the cell which is connected thereto.
At first, the source and drain bit-lines are connected to a voltage source which provides a predetermined voltage level of V.sub.1 (V.sub.1 &gt;0, and typically, around 1.5 volts), thereby pre-charging them to that predetermined voltage level V.sub.1. The voltage level V.sub.1 is selected according to a plurality of parameters, such as the memory cell characteristics, the word line voltage and the like. The voltage level V.sub.1 is typically in the range of 1-2 volts.
Then, the source bit-line is discharged to ground potential, the drain bit-line is disconnected from the V.sub.1 voltage source and is connected to a sensing amplifier, referenced 22, via a decoder 20. The voltage level which is detected on the drain bit-line is used to determine the data content of the read memory cell.
It is noted that the decoder 20 generally includes all of the electronic units which are located between the selected cell and the sensing amplifier 22.
The following is an example of a conventional method for reading the content of a selected cell. In a read procedure, one of the two selected bit lines is defined as a source and the other is defined as a drain from which the content of the cell will be read. For reading the content of memory cell 16.sub.(L+1,k), bit line 14.sub.L+1 is defined as a source and bit line 14.sub.L+2 as the drain.
Reference is now made to FIGS. 2 and 3. FIG. 2 is an illustration of a voltage versus time diagram, relating to the voltage which is applied and detected over a drain bit line. FIG. 3 is a schematic illustration of a method for detecting the content of a selected memory cell which is known in the art. The following is a description of this method.
In step 50, a plurality of bit lines are connected to a voltage source (not shown) and are thus pre-charged to a predetermined voltage level V.sub.1 (typically around 1.5 volts). These bit lines include the source bit line 14.sub.L+1, the drain-bit line 14.sub.L+2 and other bit-lines which are adjacent to the drain bit-line, such as bit-lines 14.sub.L+3 and 14.sub.L+4.
It will be appreciated by those skilled in the art that a cell experiences electrical activity when there is a voltage difference between the two bit-lines which are connected thereto. Accordingly, if bit-line 14.sub.L+3 is kept at a potential which is different than V.sub.1, then cell 16.sub.(L+2,K) will conduct current.
For example, when bit-line 14.sub.L+3 is kept at a voltage level which is lower than V.sub.1, then it is considered a source bit-line of cell 16.sub.(L+2,K), while bit-line 14.sub.L+2 is considered a drain bit-line for that cell 16.sub.(L+2,K). In a situation such as this, cell 16.sub.(L+2,K) conducts electrical current and hence, "leaks" electrical current towards bit-line 14.sub.L+2.
The electrical current which is detected from bit-line 14.sub.L+2 now includes currents received from cell 16.sub.(L+1,K) as well as from cell 16.sub.(L+2,K). Such a leakage from a neighbor cell 16.sub.(L+2,K) induces an error in the reading of cell 16.sub.(L+1,K). Furthermore, as the voltage gap between bit-lines 14.sub.L+2 and 14.sub.L+3 increases, so does the current leakage from cell 16.sub.(L+2,K), and hence the induced error. It will be appreciated by those skilled in the art that such errors significantly interfere with any reading attempt of the selected cell 16.sub.(L+1,K).
The general common approach, known in the art, is to attempt to eliminate the electrical activity within adjacent cells, such as cell 16.sub.(L+2,K), by equating the voltage on bit lines which are connected thereto. Accordingly, bit line 14.sub.L+3 is connected to a voltage source of the same electrical potential level (i.e., V.sub.1).
It is hereby noted that such leakage effects of neighbor cells also extend to other adjacent cells, located in the same row, further down the line from cell 16.sub.(L+2,K). Hence, it is recommended that an electrical potential of V.sub.1 will be applied to the bit lines which are connected thereto, such as bit-lines 14.sub.L+4.
In step 52, the source bit-line is discharged to ground, thereby establishing electrical activity within memory cell 16.sub.(L+1,K).
With reference to FIG. 2, section 30 illustrates the voltage rise, during the pre-charge step 50, which can be read from bit-line 14.sub.L+2 as it is pre-charged to V.sub.1.
In step 54, the drain bit-line 14.sub.L+2 and the neighbor bit-lines 14.sub.L+3 and 14.sub.L+4 are disconnected from the V.sub.1 voltage source. The voltage level which is read from bit-line 14.sub.L+2 can be now used to determine the state of the selected cell 16.sub.(L+1,K) as being programmed or erased (step 56).
In step 56, the sensing amplifier 22 detects the voltage level of the drain bit-line 14.sub.L+2.
It will be appreciated by those skilled in the art that a memory cell, such as FLASH, ROM, EPROM, EEPROM, and the like, exhibits greater resistance to the flow of electrons therethrough when it is in a programmed state, contrary to the situation when it is in an erased state. Accordingly, an erased cell exhibits a faster decay of the voltage, detected at the drain bit-line, than a programmed cell does.
With reference to FIG. 2, line 32 represents the voltage level decay which is detected for a programmed cell, while line 34 represents the voltage level decay which is detected for an erased cell.
In step 58, at a predetermined point in time T.sub.2, the detected voltage level (V.sub.PROGRAMMED or V.sub.ERASED) is compared against a reference level V.sub.REFERENCE. With reference to FIG. 2, line 36 represents a reference voltage profile, which reaches a reference voltage level V.sub.REFERENCE at time T.sub.2.
In step 60, the sensing amplifier determines the value of the data which is stored in the selected cell. When the detected voltage level is located above the reference level V.sub.REFERENCE, then the sensing amplifier provides an output which indicates that the cell is programmed. In this case, the detected voltage level decay is slower than the reference voltage decay.
Alternatively, when the detected voltage level is located below the reference voltage level V.sub.REFERENCE, then the sensing amplifier provides an output which indicates that the cell is erased. In this case, the detected voltage level decay is faster than the reference voltage decay.
Finally, after a predetermined period of time, T.sub.2, a programmed cell will reach a voltage level of V.sub.PROGRAMMED, an erased cell will reach a voltage level of V.sub.ERASED, and the reference voltage will reach a voltage level of V.sub.REFERENCE.
Typically, the voltage levels of V.sub.PROGRAMMED, V.sub.ERASED and V.sub.REFERENCE are around 1.5 volts and the differences V.sub.PROGRAMMED -V.sub.REFERENCE and V.sub.REFERENCE -V.sub.ERASED at T.sub.2 are within a range of 50-100 mV. Thus we obtain that: ##EQU1##
Accordingly, the portion of the relevant data signal (programmed or erased) within the overall detected signal is significantly small. Hence, extracting the encapsulated data from the detected signal is not an easy task. It will be appreciated by those skilled in the art that such a signal is considerably vulnerable to disturb effects which are induced by neighbor cells, due to leakage, therebetween.
According to the general approach, all of the array is kept at V.sub.1, where only the source bit-lines of read cells are "pulled" to ground. It is noted that pre-charging an entire cell array to V.sub.1 is a considerable task which requires large power supply units.
Another approach, known in the art, is commonly implemented for flash cell arrays. According to this approach, the array is segmented into a plurality of blocks, for example blocks of 1024 bit lines.times.32 word lines, 1024 bit lines.times.64 word lines or 1024 bit lines.times.128 word lines. This segmentation is necessary due to the programming and erasing disturbs which are related to the physical characteristics of flash cells.
Each time that a cell, in a selected block of cells, is read, a significant number of bit lines in that block of cells have to be pre-charged to a predetermined voltage level. Accordingly, the electrical current which is needed for this multiple bit-line pre-charge is significantly high. Moreover, the initiation of such a pre-charge is characterized by a sudden rise in the electrical current load. It is noted that, in order to provide the required conditions, the pre-charge mechanism has to include a high current power supply.
A conventional flash cell in a 0.35.mu. technology is characterized by a capacitance of 5 fF, per bit. A block of 1024.times.128 cells is therefore characterized by a capacitance of around 600 pF.
Conventional pre-charge mechanisms include either P-type transistors or N-type transistors. Such a pre-charge mechanism switches a bit-line between ground voltage level and an intermediate voltage level V.sub.1. Conventionally, a large number of bit-lines have to be pre-charged and equalized to a predetermined intermediate voltage level. Using N-type transistors prolongs the equalization time period at the intermediate voltage level, due to their non-low impedance.
Reducing this time period requires reducing the impedance, conventionally by enlarging the transistor, which Increases the size of the chip.
It is noted that a pre-charge structure which includes a P-type transistor and an N-type transistor is also known in the art. The P-type transistor is used for charging to intermediate voltage levels and the N-type transistor is used for charging to ground level. It is noted that such a structure consumes large chip area.
According to yet another approach, only several bit lines, adjacent to the drain bit-line, are pre-charged to V.sub.1, so as to reduce the amount of current required for each pre-charge procedure. To determine and select the neighbor bit lines, a special Y-decoder is used. A Y-decoder is a conventional device which is used to connect each of the cells outside of the array either to a pre-charge unit or to a sensing unit. When a Y-decoder receives a request to access a selected cell, it determines which of the adjacent cells, and respective bit-lines, have to participate in the pre-charge procedure. It is noted that such a mechanism is highly complicated, due to the plurality of cases which are present in such a system. Constructing such a Y-decoder consumes considerable amounts of space and resources, within the designed chip.
Furthermore, it is noted that the number of neighbor cells, which participate in the pre-charge procedure has a significant effect on the readout which is detected on the read cell drain bit-line. When the number of neighbor cells is small, there is a high probability of interference from the neighbor cells to the read cell. When the number of neighbor cells is large, then there is a large current spike.
The external power supply voltage (V.sub.CC) which is provided to the chip can be in a broad range, typically from 2.7 to 3.6 volts. It is noted that, since the internal pre-charge voltage levels have to be accurate (around 1.5 to 1.6 volts), it is necessary to design an internal, low impedance, regulated power supply unit for significantly large currents which can provide accurate pre-charge voltage for a plurality of bit-lines. Such a power supply unit requires a large amount of space and large currents to operate.
It will be appreciated by those skilled in the art that the drive current parameter I.sub.DRIVE is used to characterize the current efficiency of a given transistor, where EQU I.sub.DRIVE .varies.(V.sub.C -V.sub.T -V.sub.S).sup.2 .varies.(2.7-.vertline.0.8+0.2.vertline.-1.5).sup.2 =(0.2).sup.2 =0.04.
With this low current efficiency, the pre-charge and equalization operations of the prior art require a significant amount of time to finish, a non-ideal situation.